1. Field of the Invention
The present invention relates to semiconductor devices. In particular, it relates to a technology for forming a dummy fill used for metal CMP (chemical mechanical polishing).
2. Description of Related Art
As the design rules for semiconductor devices become finer, a metal CMP process is commonly used to planarize an interlayer insulating film in a multilayer wiring structure.
In a conventional case where the metal CMP process is applied to a semiconductor device pattern in which a large density difference lies between high density parts and low density parts, excessive polish is likely to occur in the low density parts of the pattern. In order to prevent this phenomenon and peeling of the pattern and to achieve improved planarization of the interlayer insulating film, insertion of dummy fills in the low density parts, in addition to the essentially required active traces, has been proposed (cf. Patent literature 1). A process of forming the dummy fills is varied depending on design rules for layout of a wiring pattern and the amount of data for forming a mask pattern.
(Patent Literature 1) Publication of Japanese Patent Application No. 9-306996
(Patent Literature 2) Publication of Japanese Patent Application No. 2002-373896 (FIGS. 1 and 2)
(Nonpatent Literature 1) H. P. Tuinhout, et al., “Test Structures for Investigation of Metal Coverage Effects on MOSFET Matching”, Proc. IEEE 1997 Int. Conference on Microelectronic Test Structures, Vol. 11, pp. 179-183, March 1997
(Nonpatent Literature 2) S. Lakshminarayanan et al., “Electrical Characterization of the Copper CMP Process and Deviation of Metal Layout Rules”, IEEE TRANSACTION ON SEMICONDUCTOR MANUFACTURING, VOL. 16, NO. 4, NOVEMBER 2003
(Nonpatent Literature 3) Chenting Lin, Larry Clevenger, Florian Schnabel, Fen Fen Jamin, David Dobuzinski, “Planarization of dual-damascene post-metal-CMP structures”, Interconnect Technology, 1999. IEEE International Conference, 24-26 May 1999 Page(s): 86-88
In the case of forming MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) having a relatively long gate length, e.g., around 10 μm, on a semiconductor substrate, parts of a pattern corresponding to MOSFET regions become less dense than the other parts. If the metal CMP process is applied to this case, excessive erosion is more likely to occur in the MOSFET regions and intended planarity may not possibly be obtained. From this aspect, there arises a need of providing dummy metal fills above gate electrodes of the MOSFETs having a relatively long gate length.
However, the provision of metals above the MOS transistors brings about variations of transistor characteristics, such as degradation of a drain current, as reported by Nonpatent Literature 1. That is, when the dummy fills are formed above the gate electrodes, there arises a difficulty in making the characteristics of the MOS transistors uniform.
In order to make the transistor characteristics uniform and achieve the intended effect of the metal CMP process on the MOSFETs having a relatively long gate length, Patent Literature 2 proposes to arrange the dummy fill so that its geometrical center is aligned with a center of a channel in the gate length direction. If the MOSFET is obtained in exactly the same shape as the mask dimension, it will be depicted as shown in a plan view of FIG. 45 and in a sectional view of FIG. 46 taken along the I-II line shown in FIG. 45.
In an actual manufacturing process, however, a mask for forming the metal wiring layer is misaligned. As a result of the misalignment, the structure shown in FIGS. 45 and 46 varies as shown in FIGS. 47 and 48. Specifically, the dummy fill is no longer symmetric with respect to the geometrical center GC of the gate electrode due to the mask misalignment in the gate length direction. As a result, the transistor characteristics vary depending on the direction of a current flowing between a source and a drain. The variations of transistor characteristics are not preferable particularly for a current mirror circuit and a differential input of an analog circuit in which matched transistor characteristics are essential.
If a material softer than an interlayer insulating film or a barrier metal is used as the dummy metal fill, and when the width of the dummy metal fill is increased, dishing (excessive polish) occurs. In this case, adjacent active traces are also affected. In the above-described structure, the width of the dummy metal fill is increased as the channel region is enlarged. Therefore, as shown in FIG. 49, adjacent source and drain electrodes are also polished too much due to the presence of the dummy metal fill. As a result, parasitic resistance of the source and the drain increases, thereby deteriorating the performance of the semiconductor device.